S6E1C3 Datasheet, PDF (69/107 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

S6E1C3 Series
When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=1)
Parameter
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
SCS↓→SOT delay time
SCS↑→SOT delay time
Symbol
tCSSI
tCSHI
tCSDI
tCSSE
tCSHE
tCSDE
tDSE
tDEE
Conditions
Master mode
Slave mode
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
VCC < 2.7 V
Min
Max
VCC ≥ 2.7 V
Min
Max
Unit
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50 ns
(*3)-50
(*3)+50
(*3)-50
(*3)+50 ns
3tCYCP+30
-
3tCYCP+30
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
55
-
40
ns
0
-
0
-
ns
*1: CSSU bit value × serial chip select timing operating clock cycle.
*2: CSHD bit value × serial chip select timing operating clock cycle.
*3: CSDS bit value × serial chip select timing operating clock cycle.
Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes
inactive to the time when the serial chip select pin becomes active again.
Notes:
− tCYCP indicates the APB bus clock cycle time.
For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram".
− For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.
− When the external load capacitance CL=30 pF.
Document Number: 002-00233 Rev.*B
Page 69 of 107