S6E1C3 Datasheet, PDF (59/107 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

S6E1C3 Series
− For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency and temperature have been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
11.4.6 Reset Input Characteristics
Parameter
Reset input time
Symbol
tINITX
Pin
Name
INITX
Conditions
-
11.4.7 Power-on Reset Timing
Parameter
Power supply rising time
Power supply shut down time
Time until releasing
Power-on reset
Symbol
tVCCR
tOFF
tPRT
Pin
Name
VCC
(VCC = 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Value
Min
Max
Unit
Remarks
500
-
ns
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Value
Min
Max
Unit
Remarks
0
-
ms
1
-
ms VCC < 0.2V
0.43
3.4
ms
VCC
VCC_minimum
VDH_minimum
Internal reset
CPU Operation
0.2V
t_VCCR
t_PRT
Reset active
0.2V
0.2V
t_OFF
Release
start
Glossary
 VCC_minimum : Minimum VCC of recommended operating conditions.
 VDH_minimum : Minimum detection voltage of Low-Voltage detection reset.
See "11.7 Low-Voltage Detection Characteristics".
Document Number: 002-00233 Rev.*B
Page 59 of 107