S6E1C3 Datasheet, PDF (84/107 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

S6E1C3 Series
11.5 12-bit A/D Converter
Electrical Characteristics of A/D Converter (Preliminary Values)
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Symbol Pin Name
Value
Min
Typ
Max
Unit
-
-
-
-
12
bit
-
-
- 4.5
-
4.5
LSB
-
-
- 2.5
-
+ 2.5
LSB
VZT
ANxx
- 15
-
+ 15
mV
Remarks
Full-scale transition voltage
VFST
ANxx
AVRH - 15 - AVRH + 15 mV
Conversion time*¹
1.0
-
-
VCC ≥ 2.7 V
-
-
4.0
-
-
μs 1.8 ≤ VCC < 2.7 V
10
-
-
1.65 ≤ VCC < 1.8 V
Sampling time ^*2
0.3
-
VCC ≥ 2.7 V
Ts
-
1.2
-
10
μs 1.8 ≤ VCC < 2.7 V
Compare clock cycle *³
Tcck
-
3.0
-
1.65 ≤ VCC < 1.8 V
50
-
VCC ≥ 2.7 V
200
-
1000
ns 1.8 ≤ VCC < 2.7 V
500
-
1.65 ≤ VCC < 1.8 V
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
Analog input resistance
RAIN
-
Interchannel disparity
-
-
-
-
7.5
pF
2.2
VCC ≥ 2.7 V
-
-
5.5
kΩ _{1.8 ≤ VCC < 2.7 V}
10.5
1.65 ≤ VCC < 1.8 V
-
-
4
LSB
Analog port input leak
current
-
ANxx
-
-
5
μA
Analog input voltage
-
ANxx
VSS
-
AVRH
V
Reference voltage
-
AVRH
2.7
VCC
-
VCC
V
VCC ≥ 2.7V
VCC < 2.7V
-
AVRL
VSS
-
VSS
V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The minimum conversion time is computed according to the following conditions:
VCC ≥ 2.7 V
sampling time=0.3 μs, compare time=0.7 μs
1.8 ≤ VCC < 2.7 V sampling time=1.2 μs, compare time=2.8 μs
1.65 ≤ VCC < 1.8 V sampling time=3.0 μs, compare time=7.0 μs
Ensure that the conversion time satisfies the specifications of the sampling time (tS) and compare clock cycle (tCCK).
For details of the settings of the sampling time and compare clock cycle, refer to "Chapter: A/D Converter" in "FM0+ Family
Peripheral Manual Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see "8. Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: The required sampling time varies according to the external impedance.
Set a sampling time that satisfies (Equation 1).
*3: The compare time (tC) is the result of (Equation 2).
Document Number: 002-00233 Rev.*B
Page 84 of 107