S6E1C3 Datasheet, PDF (80/107 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

S6E1C3 Series
11.4.12 I²S Timing (MFS-I2S Timing)
Master Mode Timing
Parameter
MI2SCK max frequency (*1)
I²S clock cycle time (*1)
I²S clock Duty cycle
MI2SCK↓ → MI2SWS delay
time
MI2SCK↓ → MI2SDO delay
time
MI2SDI → MI2SCK ↑ setup
time
MI2SCK ↑ → MI2SDI hold
time
MI2SCK falling time
MI2SCK rising time
Symbo
l
FMI2SCK
tICYC
∆
tSWDT
tSDDT
tDSST
tSDHT
tF
tR
Pin
Name
MI2SCKx
MI2SCKx
MI2SCKx
MI2SCKx
,
MI2SWS
x
MI2SCKx
,
MI2SDO
x
MI2SCKx
,
MI2SDIx
MI2SCKx
,
MI2SDIx
MI2SCKx
MI2SCKx
Conditions
CL=30 pF
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
VCC < 2.7 V
Min
Max
VCC ≥ 2.7 V
Min
Max
Unit
-
6.144
-
6.144 MHz
4 tCYCP
-
4 tCYCP
-
ns
45%
55%
45%
55%
-30
+30
-20
+20
ns
-30
+30
-20
+20
ns
50
-
36
-
ns
0
-
0
-
ns
-
5
-
5
ns
-
5
-
5
ns
*1: I²S clock should meet the multiple of PCLK(tICYC) and the frequency less than FMI2SCK meantime. The detail information please
refer to Chapter I²S of Communication Macro Part of Peripheral Manual.
MI2SCK
MI2SWS
and
MI2SDO
MI2SDI
VIH
VIL
tF
tSWDT,
tSDDT
VOH
VOL
VIH
VIL
tR
tDSST
VIH
VIL
tSDHT
VIH
VIL
Document Number: 002-00233 Rev.*B
Page 80 of 107