S6J3350 Datasheet, PDF (231/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
(16-2) DDR-HSSPI Interface Timing (DDR mode)
(TA: Recommended operating conditions, Vcc3=3.3 V ±0.3 V, VSS=DVSS=AVSS=0.0 V)
Parameter
HSSPI clock cycle
M_SCLK↑ ->
delayed sample
clock↑
M_SDATA -> delayed
sample clock↑
Input setup time
delayed sample
clock↑ -> M_SDATA
Input hold time
M_SCLK↑ ->
M_SDATA
Output delay time
M_SCLK↑ ->
M_SDATA
Output hold time
M_SCLK↑ ->
M_SSEL
Output delay time
M_SCLK↑ ->
M_SSEL
Output hold time
Symb
ol
tcyc
tspcnt
tisdata
tihdata
toddata
tohdata
todsel
tohsel
Pin Name
M_SCLK0
M_SDATA0_0-3
M_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
M_SSEL0, 1
M_SSEL0, 1
Conditions
(CL = 20pF,
IOL=-10mA,
IOH=10mA),
Value
Min
Max
10
-
0
tcyc
Unit Remarks
ns
ns
1.0
-
ns
1.0
-
ns
-
3.5
ns
tcyc/2-1.5n
s
1.5
-
ns
-
7.0
ns tcyc -3.0ns
3.0
-
ns
Notes: This is target spec.
MG_S_CSCLKL0K0
V_OH
t_cyc
V_OL
V_OH
delayed
sample clock
t_spcnt
V_OH
M_^GS^_D^SA^DTA^A0^T_^A0⁰-^_3⁰, ^-3,
M_GS_DSADTAA1T_A01-_30-3
V_IH ^{tisdata tihdata} _VIH
valid
(input timing)
V_IL
V_IL
t_oddata
t_{oddata VOH}
t_ohdata
t_{ohdata VOH}
M_^GS^_D^SA^DT^AA^T0^A_0⁰-^_3⁰, ^-3,
M_GS_DSADTAT1A_01-_30-3
valid
valid
(output timing)
V_OL
V_OL
t_odsel
V_OH
t_ohsel
V_OH
M_^GS^SS^SE^EL^L0,⁰1^{, 1}
(output timing)
valid
V_OL
V_OL
Document Number: 002-10634 Rev.**
Page 231 of 249