S6J3350 Datasheet, PDF (183/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
Parameter
Internal clock
frequency
Symbol
FCLK_CD3B0
FCLK_CD3B1
FCLK_CD4
FCLK_CD4A0
FCLK_CD4A1
FCLK_CD4B0
FCLK_CD4B1
FCLK_CD5
FCLK_CD5A0
FCLK_CD5A1
FCLK_CD5B0
FCLK_CD5B1
FCLK_HSSPI
FCLK_SYSC0H
FCLK_COMH
FCLK_RAM0H
FCLK_RAM1H
FCLK_SYSC0P
FCLK_COMP
Max *1
80
80
200
200
200
200
200
240
120
120
60
60
200
80
80
80
80
80
80
Value
Max *2
80
80
200
200
200
200
200
240
120
120
60
60
200
66.7
66.7
66.7
66.7
66.7
66.7
Max *3
80
80
200
200
200
200
200
240
120
120
60
60
200
60
60
60
60
60
60
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Remarks
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Notes:
- *1: Target maximum clock frequencies when CPU clock = 240MHz
- *2: Target maximum clock frequencies when CPU clock = 200MHz
- *3: Target maximum clock frequencies when CPU clock =180MHz
- Note that Ta=125 condition is not supported in *1 and *2 use case.
Please set to *3 when device Ta = 125.
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following restrictions.
‐On the presumption that the modulation mode of SSCG_PLL is used with down spread,
the MAX value of the frequency is standardized.
‐This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
Document Number: 002-10634 Rev.**
Page 183 of 249