S6J3350 Datasheet, PDF (10/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
3. Product Description
3.1 Overview
This chapter explains the product features of S6J3350 series. The description of this chapter should precede the duplicated
description on Traveo^TM Platform hardware manual.
3.2 Product description
The table shows features.
Table 3-1
Feature
Technology
Description
40nm CMOS technology with embedded FLASH
Fully automotive qualified according to ISO/TS 16949 and AEC-Q100
Developed according to ISO26262, safety target ASIL-B
Functional Safety
Peripherals
Power Domain (PD)
Debug and Trace
System Control
Clock
Clock Supervisor
Reset
The product series has some functional safety features suited for ASIL-B application.
See function list.
See the Traveo^TM Platform hardware manual and chapter STATE TRANSITION in detail.
The product series supports the power off control of PD1, PD2 (including PD3 and 5), and PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the product
series, and "0" is always read from the reset factor flags of them.
This series doesn't support partial wakeup for PD6.
See the Traveo^TM Platform hardware manual in detail.
− Standard 5-pin JTAG interface
− 4kB Embedded Trace Buffer
4-bit trace support for TEQFP package.
See the Traveo^TM Platform hardware manual in detail.
Main and sub oscillator is available.
− A wide range of 3.6 - 4MHz is available for main oscillator
− 32KHz is available for sub oscillator
Sub clock is enable/disable by register settings
See the Traveo^TM Platform hardware manual in detail.
CLK_CLKO (Clock Output Function) is supported.
See the Traveo^TM Platform hardware manual in detail.
This product series doesn’t support clock supervisor output port. (Related register and internal
circuit is implemented.)
Based on Cortex R5F platform
Following resets are not mounted on this device.
− INITX
− SRSTX
Hardware watchdog
See the Traveo^TM Platform hardware manual in detail.
Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the
bit
ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1).
The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and
internal circuit is implemented.)
Document Number: 002-10634 Rev.**
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