S6J3350 Datasheet, PDF (208/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
Parameter Symbol
Pin Name
Conditions
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
Master
SCK8 to SCK12
mode
SCS0x, SCS1x,
round
SCS2x_1,
operation
SCS3x_1, SCS4,
(CL=20pF,
SCK ↓ → SCS ↑
SCS8x to SCS12x
SCK16 to SCK17
IOL=-5mA,
IOH=5mA)
clock switching
tSCC
SCS16x to SCS17x
time
Master
mode
round
SCK2_0, SCK3_0,
operation
SCS2x_0, SCS3x_0
(CL =
20pF,
IOL=-10mA,
IOH=10mA)
*1: _{tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock}
*2: _{tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock}
*3: _{tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock}
For details on ^*1, ^*2, and ^*3 above, see the hardware manual.
Value
Min
Max
4tCLK_LCPnA*4
+0
4tCLK_LCPnA*
4 ₊₁₅
4tCLK_COMP +0
4tCLK_COMP
+15
4tCLK_LCPnA*4
+0
4tCLK_LCPnA*
4 ₊₁₀
*4 tCLK_LCPnA n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Notes:
− This is the AC characteristic in CLK synchronized mode.
− CL is the load capacitance applied to pins during testing.
− The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual
Unit
ns
ns
ns
Remarks
SCS output ^VOH
t_CSSI
SCK output
V_OL
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
Master mode
V_OH
t_CSHI
t_CSDI
V_OL
V_OH
Document Number: 002-10634 Rev.**
Page 208 of 249