S6J3350 Datasheet, PDF (196/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
Parameter
Symbol
Pin Name
Serial clock
"H" pulse width
tSHSL
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
Serial clock
"L" pulse width
tSLSH
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↑ → SOT
delay time
tSHOVE
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
Valid SIN → SCK
SCK0 to SCK4,
↓
setup time
tIVSLE
SCK8 to SCK12,
SCK16 to SCK17
SCK ↓ → Valid
SIN0 to SIN4,
SIN
hold time
tSLIXE
SIN8 to SIN12,
SIN16 to SIN17
SCK0 to SCK4,
SCK falling time
tF
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK rising time
tR
SCK8 to SCK12
SCK16 to SCK17
*1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Condition
s
Value
Min
4tCLK_LCPnA*1
4tCLK_COMP
4tCLK_LCPnA*1
4tCLK_COMP
Max
-
-
-
-
-
40
Slave
Mode
(CL=20pF,
IOL=-5mA,
IOH=5mA)
10
-
10
-
-
5
-
5
Notes:
− This table provides the alternate current standard for CLK synchronous mode.
− CL is the load capability value connected to the pin at the test time.
− The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Unit Remarks
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK
SOT
SIN
t_SOVLI
V_OH
V_OL
V_OL
t_SCYC
V_OH
t_SHOVI
V_OL
V_OH
V_OL
t_IVSLI
V_IH
V_IL
t_SLIXI
V_IH
V_IL
Master mode
Document Number: 002-10634 Rev.**
Page 196 of 249