S6J3350 Datasheet, PDF (189/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
CSIO timing (SMR:MD2-0=0b010)
(1) Normal synchronous transfer (SCR:SPI=0) and mark level "H" of serial clock output (SMR:SCINV=0)
(TA: Recommended operating conditions, Vcc3=3.3 V ±0.3V, Vcc5=DVcc=5.0 V ±10% /3.3 V ±0.3V,
Vcc53=5.0 V ±10% / 3.3 V ±0.3V, VSS=DVSS=0.0 V, VCC12=1.15V ±0.06V)
Parameter
Symbol
Pin Name
Condition
s
Value
Min
Max
Unit Remarks
Serial clock
cycle time
tSCYC
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12
8tCLK_LCPnA*1
-
ns
-
SCK16 to SCK17
8tCLK_COMP
-
ns
SCK ↓ → SOT
delay time
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
tSLOVI
SCK16 to SCK17
SOT0, SOT1,
Master
Mode
-30
SOT2_1,
(CL = 20pF,
SOT3_1, SOT4,
IOL=-5mA,
SOT8 to SOT12,
IOH=5mA)
SOT16 to SOT17
+30
ns
Valid SIN → SCK
↑
setup time
tIVSHI
SCK ↑→ Valid SIN
hold time
tSHIXI
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0, SIN1, SIN2_1,
SIN3_1, SIN4,
SIN8 to SIN12,
SIN16 to SIN17
40
-
ns
0
-
ns
Serial clock
cycle time
tSCYC
SCK2_0, SCK3_0
2tCLK_LCPnA*1
-
ns
SCK ↓ → SOT
delay time
tSLOVI
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
Master
Mode
-7.5
(CL = 20pF,
Valid SIN → SCK
IOL=-10mA,
↑
tIVSHI
IOH=10mA)
10
setup time
SCK2_0, SCK3_0,
SCK ↑→ Valid SIN
hold time
tSHIXI
SIN2_0, SIN3_0
0
+7.5
ns
-
-
ns
-
ns
Document Number: 002-10634 Rev.**
Page 189 of 249