S6J3350 Datasheet, PDF (198/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
(4) SPI supported (SCR:SPI=1), and mark level "L" of serial clock output (SMR:SCINV=1)
(TA: Recommended operating conditions, Vcc3=3.3 V ±0.3V, Vcc5=DVcc=5.0 V ±10% /3.3V ±0.3V,
Vcc53=5.0 V ±10% / 3.3 V ±0.3V, VSS=DVSS=0.0 V, VCC12=1.15V ±0.06V)
Parameter
Symbol
Serial clock
cycle time
tSCYC
SCK ↓ -> SOT
delay time
tSLOVI
Valid SIN -> SCK ↑
setup time
tIVSHI
SCK ↑ -> Valid SIN
hold time
tSHIXI
SOT -> SCK ↑
delay time
tSOVHI
Serial clock
cycle time
SCK ↓ -> SOT
delay time
Valid SIN -> SCK ↑
setup time
SCK ↑ -> Valid SIN
hold time
SOT -> SCK ↑
delay time
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
Pin Name
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0, SOT1,
SOT2_1,
SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0, SIN1, SIN2_1,
SIN3_1, SIN4,
SIN8 to SIN12,
SIN16 to SIN17
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0, SOT1,
SOT2_1,
SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK16 to SCK17
SOT16 to SOT17
SCK2_0, SCK3_0
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
SCK2_0, SCK3_0,
SIN2_0, SIN3_0
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
Condition
s
Master
Mode
(CL = 20pF,
IOL=-5mA,
IOH=5mA)
Master
Mode
(CL = 20pF,
IOL=-10mA,
IOH=10mA)
Value
Min
Max
8tCLK_LCPnA*1
-
8tCLK_COMP
-
-30
+30
40
-
0
-
4tCLK_LCPnA*1
-30
-
4tCLK_COMP
-30
2tCLK_LCPnA*1
-7.5
10
0
tCLK_LCPnA*1 -
7.5
-
-
+7.5
-
-
-
Unit Remarks
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
ns
Document Number: 002-10634 Rev.**
Page 198 of 249