S6J3350 Datasheet, PDF (226/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
9.1.4.14 External bus interface timing
Clock output timing
(TA: Recommended operating conditions, Vcc53=5.0 V ±10%, VSS=0.0 V)
(External load capacitance 16pF)
Parameter
Symbol
Pin Name
Conditions
Cycle time
Clock high width ^*1
tCYC
tCHCL
MCLK
MCLK
2mA is
selected in
ODR bit in
Clock low width ^*2
tCLCH MCLK
PPC_PCFG
R register.
*1: If division-ratio is even value, dH is equivalent to 0.5.
Value
Min
Max
62.5
-
dHtcyc - 7 dHtcyc + 7
dLtcyc - 7 dLtcyc + 7
Unit
ns
ns
ns
Remarks
Otherwise, dH is calculated as the following.
dH = The number rounding "division-ratio x 0.5" down to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dH is calculated as 0.429.
*2: If division-ratio is even value, dL is equivalent to 0.5.
Otherwise, dL is calculated as the following.
dL = The number rounding "division-ratio x 0.5" up to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dL is calculated as 0.571.
− Clock output timing
Document Number: 002-10634 Rev.**
Page 226 of 249