S6J3350 Datasheet, PDF (230/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
9.1.4.15 DDR-HSSPI
(16-1) DDR-HSSPI Interface Timing (SDR mode)
(TA: Recommended operating conditions, Vcc3=3.3 V ±0.3 V, VSS=DVSS=AVSS=0.0 V)
Parameter
HSSPI clock cycle
M_SCLK↑ ->
delayed sample
clock↑
M_SDATA -> delayed
sample clock↑
Input setup time
Symbol
tcyc
tspcnt
tisdata
Pin Name
M_SCLK0
-
M_SDATA0_0-3
M_SDATA1_0-3
Conditions
Value
Min
Max
10
-
0
tcyc
Unit Remarks
ns
ns
3.5
-
ns
delayed sample
clock↑ -> M_SDATA
Input hold time
tihdata
M_SDATA0_0-3
M_SDATA1_0-3 _{(CL = 20pF,}
2.0
M_SCLK↑ ->
M_SDATA
Output delay time
toddata
M_SDATA0_0-3
M_SDATA1_0-3
IOL=-10mA,
IOH=10mA),
-
-
ns
6.5
ns tcyc -3.5ns
M_SCLK↑ ->
M_SDATA
Output hold time
tohdata
M_SDATA0_0-3
M_SDATA1_0-3
3.5
-
ns
M_SCLK↑ -> M_SSEL
Output delay time
todsel
M_SCLK↑ -> M_SSEL
Output hold time
tohsel
M_SSEL0, 1
M_SSEL0, 1
-
5.5
ns tcyc -4.5ns
4.5
-
ns
Notes: This is target spec.
MG_SSCLLKK00
V_OH
t_cyc
V_OH
delayed
sample clock
M^G_^_S^SD^DA^AT^TA^A0_⁰0^_-⁰3^-,^3,
MG__SSDDAATTAA1_10_-03-3
(input timing)
M^G_^_S^SD^DA^AT^TA^A0⁰_^_0⁰-3^-,^3,
MG__SSDDAATTAA11__00-3-3
(output timing)
G_MS_{_S}SE_SL_E0_L,_0,1₁
(output timing)
t_spcnt
V_OH
V_IH ^{tisdata tihdata} _VIH
valid
V_IL
V_IL
t_{oddata VOH}
t_odsel
V_OL
V_OH
V_OL
valid
t_ohdata
valid
t_ohsel
V_OH
V_OL
V_OH
V_OL
Document Number: 002-10634 Rev.**
Page 230 of 249