S6J3350 Datasheet, PDF (193/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
Parameter
Symbol
Pin Name
Serial clock
cycle time
tSCYC
SCK2_0, SCK3_0
SCK ↓ → SOT
delay time
tSHOVI
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
Valid SIN → SCK
↑
setup time
SCK ↑→ Valid SIN
hold time
tIVSLI
tSLIXI
SCK2_0, SCK3_0,
SIN2_0, SIN3_0
Serial clock
"H" pulse width
tSHSL
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
Serial clock
"L" pulse width
tSLSH
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK ↑ → SOT
delay time
tSHOVE
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
Valid SIN → SCK
↓
setup time
SCK ↓ → Valid
SIN
hold time
tIVSLE
tSLIXE
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SIN8 to SIN12,
SIN16 to SIN17
SCK0 to SCK4,
SCK falling time
tF
SCK8 to SCK12,
SCK16 to SCK17
SCK rising time
SCK0 to SCK4,
tR
SCK8 to SCK12,
SCK16 to SCK17
*1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Condition
s
Master
Mode
(CL = 20pF,
IOL=-10mA,
IOH=10mA)
Value
Min
2tCLK_LCPnA*1
Max
-
-7.5
+7.5
10
-
0
-
4tCLK_LCPnA*1
-
4tCLK_COMP
-
4tCLK_LCPnA*1
-
4tCLK_COMP
-
-
40
Slave
Mode
(CL=20pF,
IOL=-5mA,
IOH=5mA)
10
-
10
-
-
5
-
5
Notes:
− This table provides the alternate current standard for CLK synchronous mode.
− CL is the load capability value connected to the pin at the test time.
− The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Unit Remarks
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document Number: 002-10634 Rev.**
Page 193 of 249