S6J3350 Datasheet, PDF (11/249 Pages) Cypress Semiconductor – 32-bit Microcontroller Spansion® TraveoTM Family

PRELIMINARY
S6J3350 Series
Feature
Standby mode
PLL / SSCG PLL
External Interrupts
NMI
Memory Protection
Peripheral Protection
Internal Memories
System SRAM
Internal Memories
TCRAM
Internal Memories
Backup RAM
Description
See the Traveo^TM Platform hardware manual in detail.
Standby mode with 5V (or 3V) single external power supply is available.
Turning off the 1.2V external power supply in standby mode is available.
The long term pulse of the indicator PWM can be outputted during RTC Standby mode.
See the Traveo^TM Platform hardware manual in detail.
Use case assumption is following.
PLL
− Peripherals
− Trace clock
SSCG
− CPU core
− Hyper BUS
− DDR-HSSPI
Down spread mode is only supported and available.
See the Traveo^TM Platform hardware manual in detail.
See the Traveo^TM Platform hardware manual in detail.
1 NMI pin.
MPU16 AHB: See the Traveo^TM Platform hardware manual in detail.
MPU for AXI: ch.0
MPU for AHB: ch.1
Additional MPU for Ethernet AVB. They are described on the chapter of MPU for AHB and MPU
for AXI
To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,
− Lock: 0x112ABB56
− Unlock: 0xACCABB56
See the Traveo^TM Platform hardware manual in detail.
Protected peripherals are described in the base address map.
384kByte
1 wait cycle is necessary for RAM read at over 120MHz.
128kByte
32kByte
Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the
memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM is
not supported and cannot be used.
Document Number: 002-10634 Rev.**
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