SM55161A Datasheet, PDF (6/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
TABLE 2: PIN DESCRIPTIONS VS. OPERATIONAL MODE
PIN
A0-A8
CASL\,
CASU\
DQ
DSF
RAS\
DRAM
Row, column address
Column-address strobe, DQ output enable
DRAM data I/O, write mask
Block-write enable
Write-mask-register load enable
Color-register load enable
CBR (option reset)
Row-address strobe
SE\
SC
SQ
TRG\
WE\
QSF
DQ output enable
Write enable, write-pre-bit enable
Special-function output
TRANSFER
Row address, Tap point
Tap-address strobe
Split-register-transfer enable
SAM
Row-address strobe
Transfer enable
SQ output enable,
QSF output enable
Serial clock
Serial-data output
Serial-register status
Either make no external connection or tie to
NC/GND _{system GND (VSS)}
V_CC1
V_SS1
5V supply
Ground
NOTES: 1. For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground.
address (A0–A8)
Eighteen address bits are required to decode each one of
the 262 144 storage cell locations. Nine row-address bits are set
up on pins A0–A8 and latched onto the chip on the falling edge
of RAS\. Nine column-address bits are set up on pins A0–A8
and latched onto the chip on the first falling edge of CASx\. All
addresses must be stable on or before the falling edge of RAS\
and the first falling edge of CASx\.
During the full-register-transfer read operation, the states
of A0–A8 are latched on the falling edge of RAS\ to select one
of the 512 rows where the transfer occurs. At the first falling
edge of CASx\, the column-address bits A0–A8 are latched.
The most significant column-address bit (A8) selects which
half of the row is transferred to the SAM. The appropriate 8-bit
column address (A0–A8) selects one of 512 tap points (starting
positions) for the serial-data output.
During the split-register-transfer read operation, an
internal counter selects which half of the register is used. If the
high half of the SAM is currently in use, the low half of the
SAM is loaded with the low half of the DRAM half row and vice
versa. Column address (A8) selects the DRAM half row. The
remaining eight address bits (A0–A7) are used to select one of
256 possible starting locations within the SAM.
row-address strobe (RAS\)
RAS\ is similar to a chip enable so that all DRAM cycles
and transfer cycles are initiated by the falling edge of RAS\.
RAS\ is a control input that latches the states of the row
address, WE\, TRG\, CASL\, CASU\, and DSF onto the chip to
invoke DRAM and transfer-read/write functions of the
SMJ55161A.
column-address strobe (CASL, CASU)
CASL\ and CASU\ are control inputs that latch the states
of the column address and DSF to control DRAM and transfer
functions of the SMJ55161A. CASx\ also acts as output enable
for the DRAM output pins DQ0–DQ15. In DRAM operation,
CASL\ enables data to be written to or read from the lower byte
(DQ0–DQ7), and CASU\ enables data to be written to or from
the upper byte (DQ8–DQ15). In transfer operations, address
bits A0–A8 are latched at the first falling edge of CASx\ as the
start position (tap) for the serial-data output (SQ0–SQ15).
SMJ55161A
Rev. 1.6 03/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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