SM55161A Datasheet, PDF (13/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
write-per-bit
The write-per-bit feature allows masking any combination of
the 16 DQs on any write cycle. The write-per-bit operation is
invoked when WE\ is held low on the falling edge of RAS\. If
WE\ is held high on the falling edge of RAS\, the write opera-
tion is performed without any masking. The SMJ55161A offers
two write-per-bit modes: nonpersistent write-per-bit and per-
sistent write-per-bit.
nonpersistent write-per-bit
When WE\ is low on the falling edge of RAS\, the write mask is
reloaded. A 16-bit binary code (the write-per-bit mask) is input
to the device through the DQ pins and latched on the falling
edge of RAS\. The write-per-bit mask selects which of the 16
I/Os are to be written and which are not. After RAS\ has latched
the on-chip write-per-bit mask, input data is driven onto the DQ
pins and is latched on either the first falling edge of CASx\ or
the falling edge of WE\, whichever occurs later. CASL\ enables
the lower byte (DQ0–DQ7) to be written through the mask and
CASU\ enables the upper byte (DQ8–DQ15) to be written
through the mask. If a data low (write mask = 0) is strobed into
a particular I/O pin on the falling edge of RAS\, data is not
written to that I/O. If a data high (write mask = 1) is strobed into
a particular I/O pin on the falling edge of RAS\, data is written
to that I/O (see Figure 7).
FIGURE 7: Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
SMJ55161A
Rev. 1.6 03/05
13
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.