SM55161A Datasheet, PDF (29/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)¹
PARAMETER
Delay time, RAS\ high to last (most significant) rising edge of SC
before boundary switch during split-register-transfer read cycles
Delay time, CASx\ low to TRG\ high in read-time-transfer read
cycles
Delay time, column address to first SC in early-load-transfer read
cycles
Delay time, column address to TRG\ high in real-time-transfer read
cycles
-70
SYMBOL MIN MAX
t_d(RHMS) 20
t_d(CLTH) 17
t_d(CASH) 25
t_d(CAGH) 20
-75
MIN MAX
20
15
28
20
-80
MIN MAX
20
15
30
20
UNIT
ns
ns
ns
ns
Delay time, data to CASx\ low
t_d(DCL) 0
0
0
ns
Delay time, data to TRG\ low
t_d(DGL) 0
0
0
ns
Delay time, last (most significant) rising edge of SC to RAS\ low
before boundary switch during split-register-transfer read cycles
t_d(MSRL) 20
20
20
ns
Delay time, last (127 or 255) rising edge of SC to QSF switching at
the boundary during split-register-transfer read cycles¹⁵
t_d(SCQSF)
25
28
30 ns
Delay time, CASx\ low to QSF switching in transfer-read cycles^{15 t}d(CLQSF)
30
33
35 ns
Delay time, TRG\ high to QSF switching in transfer-read cycles^{15 t}d(GHQSF)
25
28
30 ns
Delay time, RAS\ lwo to QSF switching in transfer-read cycles¹⁵
t_d(RLQSF)
70
73
75 ns
Refresh time interval, memory
t_rf(MA)
8
8
8 ms
Transition time
t_t
3 25 3 25 3 25 ns
NOTE:
1. Timing measurements are referenced to V_IL MAX and V_IH MIN.
2. Cycle time assumes tt = 3 ns.
3. In a read-modify-write cycle, t_d(CLWL) and t_su(WCH) must be observed. Depending on the transition times, this can require additional CASx\
low time [t_w(CL)].
4. In a read-modify-write cycle, t_d(RLWL) and t_su(WRH) must be observed. Depending on the transition times, this can require additional RAS\
low time [t_w(RL)].
5. The minimum value is measured when t_d(RLCL) is set to t_d(RLCL) MIN as a reference.
6. Either t_h(RHrd) or t_d(CHrd) must be satisfied for a read cycle.
7. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
8. CBR refresh operation only.
9. Read-modify-write operation only.
10. TRG\ must disable the output buffers prior to applying data to the DQ pins.
11. The maximum value is specified only to assure RAS\ access time.
12. Real-time-load transfer read or late-load-transfer read cycle only.
13. Early-load-transfer read cycle only.
14. Full-register-(read) transfer cycles only.
15. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is
V_OH / V_OL = 2 V/0.8 V.
SMJ55161A
Rev. 1.6 03/05
29
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.