SM55161A Datasheet, PDF (5/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
TABLE 1: DRAM & SAM FUNCTIONS
RAS\ FALL
CASx\
FALL
FUNCTION
CASx\^{2 TRG\ WE\ DSF DSF}
Reserved (do not use)
L
CBR refresh (no reset) and stop-
point set⁴
L
CBR refresh (option reset)⁶
L
CBR refresh (no reset)⁷
L
L
L
L
X
X
L
H
X
X
H
L
X
X
H
H
X
ADDRESS
RAS\ _CASX\³
X
X
Stop
point⁵
X
X
X
X
X
DQ0-DQ15¹
RAS\
X
CASL\
CASU\
WE\
X
MNE
CODE
---
X
X CBRS
X
X CBR
X
X CBRN
Full-register-transfer read
H
L
H
L
X
Row Tap
Address Point
X
X
RT
Split-register-transfer read
H
L
H
H
X
Row Tap
Address Point
X
X SRT
DRAM write
(nonpersistent write-per-bit)
H
H
L
L
L
Row Column Write
Address Address Mask
Valid
Data
RWM
DRAM block write
(nonpersistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A3-A8
Write
Mask
Column
Mask
BWM
DRAM write
(persistent write-per-bit)
H
H
L
L
L
Row Column
Address Address
X
Valid
Data
RWM
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A3-A8
X
Column
Mask
BWM
DRAM write (nonmasked)
H
H
H
L
L
Row Column
Address Address
X
Valid
Data
RW
DRAM block write (nonmasked)
H
H
H
L
H
Row
Address
Block
Address
A3-A8
X
Column
Mask
BW
Load write-mask register⁸
H
H
H
H
L
Refresh
Address
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Address
X
X
Color
Data
LCR
Masked Write Transfer⁹
H
L
L
L
X
Row Tap
Address Point
Write
Mask
X
MWT
Masked Split Write Transfer⁹
H
L
L
H
X
Row Tap
Address Point
Write
Mask
X MSWT
Masked Flash Write Transfer⁹
H
H
L
H
X
Row
Address
X
Write
Mask
---
FWM
LEGEND:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X = Don’t Care
NOTES:
1. DQ0–DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later.
2. Logic L is selected when either or both CASL\ and CASU\ are low.
3. The column address and block address are latched on the first falling edge of CASx\.
4. CBRS cycle should be performed immediately after the power-up initialization cycle.
5. A0–A3, A8: don’t care; A4–A7: stop-point code
6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option
reset) cycle.
9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.
SMJ55161A
Rev. 1.6 03/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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