SM55161A Datasheet, PDF (39/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
FIGURE 32: ENHANCED-PAGE-MODE WRITE-CYCLE TIMING
NOTES:
A. Referenced to the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. To ensure page-mode cycle time, TRG\ must remain high throughout the entire page-mode operation if the late write
feature is used. If the early write-cycle timing is used, the state of TRG\ is a don’t care after the minimum period t_h(TRG) from the falling
edge of RAS\..
TABLE 10: ENHANCED-PAGE-MODE WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
2
3
4
5
Write operation (nonmasked)
L
L
H
Don't Care Valid Data
Write operation with nonpersistent write-per-bit
L
L
L
Write Mask Valid Data
Write operation with persistent write-per-bit
L
L
L
Don't Care Valid Data
Load-write mask on either the first falling edge of CASx\
or the falling edge of WE\, whichever occurs later.¹
H
L
H
Don't Care Write Mask
NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
a don’t care during this cycle.
SMJ55161A
Rev. 1.6 03/05
39
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.