SM55161A Datasheet, PDF (23/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
split-register programmable stop point
(continued)
Stop-point mode is not active until the CBRS cycle is
initiated. The CBRS operation is enabled by holding CASx\ and
WE\ low and DSF high on the falling edge of RAS\. The falling
edge of RAS\ also latches row addresses A4–A7 which are
used to define the SAM’s partition length. The other row-
address inputs are don’t cares. Stop-point mode should be
initiated after the initialization cycles are performed
(see Table 5).
In stop-point mode, the tap point loaded during the split-
register-transfer read cycle determines the SAM partition in
which the serial output begins and at which stop point the
serial output stops coming from one half of the SAM and
switches to the opposite half of the SAM (see Figure 23).
The stop-point mode of the previous revision 55161 is
designed to be compatible with both 256-bit SAM and 512-bit
SAM devices like the 55161A.
IMPORTANT: For proper device operation, a stop-point-
mode (CBRS) cycle should be initiated immediately after the
power-up initialization cycles are performed.
TABLE 5: Programming Code for Stop-Point Mode
MAX
PARTITION
LENGTH
16
32
64
128
256
ADDRESS AT RAS\ IN CBRS CYCLE NUMBER OF
PARTITIONS
STOP-POINT LOCATIONS
A8 A7 A6 A5 A4 A0 - A3
X
L
L
L
L
X
16
31, 63, 95, 127, 159, 191, 223, 255, 287,
319, 351, 383, 415, 447, 479, 511
X
L
L
L
H
X
8
63, 127, 191, 255, 319, 383, 447, 511
X
L
L
H
H
X
4
127, 255, 383, 511
X LHHH
X
2
255, 511
XHHHH
X
1
255
FIGURE 23: Example of Split-Register Operation With Programmable
Stop Points
SMJ55161A
Rev. 1.6 03/05
23
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