SM55161A Datasheet, PDF (19/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
DRAM-to-SAM transfer operation
During the DRAM-to-SAM transfer operation, one row
(512 columns) in the DRAM array is selected to be transferred
to the 512-bit serial-data register. The transfer operation is
invoked by TRG\ being brought low and WE\ being held high
on the falling edge of RAS\. The state of DSF, which is latched
on the falling edge of RAS\, determines whether the full-
register-transfer read operation or the split-register-transfer read
operation is performed (see Table 4).
full-register-transfer read
A full-register-transfer read operation loads data from a
selected half of a row in the DRAM into the SAM. TRG\ is
brought low and latched at the falling edge of RAS\. Nine row-
address bits (A0–A8) are also latched at the falling edge of
RAS\ to select one of the 512 rows available for the transfer.
The nine column-address bits (A0– A8) are latched at the first
falling edge of CASx\. Address bits A0–A8 select one of the
SAM’s 512 available tap points from which the serial data is
read out.
A full-register-transfer read can be performed in three ways:
early load, real-time load (or midline load), or late load. Each of
these offers the flexibility of controlling the TRG\ trailing edge
in the full-register-transfer read cycle (see Figure 15).
TABLE 4: SAM Fuction Table
FUNCTION
RAS\ FALL
CASx\^{1 TRG\ WE\}
Full-register-transfer Read
H
L
H
CASx\
FALL
ADDRESS
DQ0-DQ15 _MNE
DSF
DSF
RAS\
CASX\
RAS\
CASx\ CODE
WE\
L
X
Row Tap
Address Point
X
X
RT
Split-register-transfer Read
LEGEND:
X = Don’t Care
H
L
H
H
X
Row Tap
Address Point
X
X SRT
NOTES:
1. Logic L is selected when either CASL\ or CASU\ are low.
FIGURE 15: Example of Full-Register-Transfer Read Operations
SMJ55161A
Rev. 1.6 03/05
19
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