SM55161A Datasheet, PDF (20/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
split-register-transfer read
The SMJ55161A features two types of bidirectional data
transfer capability between DRAM and SAM.
1) Conventional (non split) transfer: 512 words by 16 bits of
data can be loaded from DRAM to SAM (Read transfer), or
from SAM to DRAM (write transfer).
2) Split transfer: 256 words by 16 bits of data can be loaded from
the lower/upper half of the DRAM to the lower/uppper half of
the SAM (Split read transfer), or from the lower/upper half to
SAM to the lower/upper half of DRAM (Split write transfer).
The conventional transfer and split transfer modes are
controlled by the DSF input signal. Data transfer is invoked by
holding the TRG\ signal “low” at the falling edge of RAS\.
The SMJ55161A supports 4 types of transfer operations:
Read transfer, Split read transfer, Write transfer and Split write
transfer as shown in the truth table. The type of transfer
operation is determined by the state of CAS\, WE\, and DSF
latched at the falling edge of RAS\. During conventional
transfer operations, the SAM port is switched from input to
output mode (Read transfer), or output to input mode (Write
transfer). It remains unchanged during split transfer operation
(Split read transfer or Split write transfer).
Both DRAM and SAM are divided by the most significant
row address (AX8), as shown in Figure 16. Therefore, no data
transfer between AX8=0 side DRAM and AX8=1 side DRAM
can be provided through the SAM. Care must be taken if the
split read transfer on AX8=1 side (or AX8=0 side) is provided
after the read transfer or the split read transfer, is provided on
AX8=0 side (or AX8=1 side).
QSF indicates which half of the register is being accessed
during serial-access operation. When QSF is low, the serial-
address pointer is accessing the lower (least significant) 256
bits of the SAM. When QSF is high, the pointer is accessing
the higher (most significant) 256 bits of the SAM. QSF changes
state upon completing a full-register-transfer-read cycle. The
tap point loaded during the current transfer cycle determines
the state of QSF. QSF also changes state when a boundary
between two register halves is reached.
FIGURE 16: DRAM and SAM Configuration
SMJ55161A
Rev. 1.6 03/05
20
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