SM55161A Datasheet, PDF (54/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
FIGURE 44: FULL-REGISTER TRANSFER READ-TIMING, REAL-TIME
LOAD OPERATION/LATE-LOAD OPERATION
NOTES:
A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
to from the 512 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive
transition of SC.
C. A0–A8.
D. Late load operation is defined as t_d(THRH) < 0 ns.
SMJ55161A
Rev. 1.6 03/05
54
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