SM55161A Datasheet, PDF (41/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
FIGURE 34: ENHANCED-PAGE-MODE READ-/WRITE-CYCLE TIMING
NOTES:
A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write
mode (normal, block write, etc.).
SMJ55161A
Rev. 1.6 03/05
41
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