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SM55161A Datasheet, PDF (27/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM
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Austin Semiconductor, Inc.
VRAM
SM55161A
Production
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1
PARAMETER
-70
-75
-80
SYMBOL MIN MAX MIN MAX MIN MAX UNIT
Cycle time, read
tc(rd) 124
140
150
ns
Cycle time, write
tc(W) 124
140
150
ns
Cycle time, read-modify-write
tc(rdW) 170
188
200
ns
Cycle time, page-mode read, write
tc(P)
35
48
50
ns
Cycle time, page-mode read-modify-write
tc(RDWP) 74
88
90
ns
Cycle time, transfer read
Cycle time, serial clock2
tc(TRD) 130
140
150
ns
tc(SC) 20
24
30
ns
Pulse duration, CASx\ high
Pulse duration, CASx\ low3
tw(CH)
tw(CL)
10
10
10
ns
15 10,000 20 10,000 20 10,000 ns
Pulse duration, RAS\ high
Pulse duration, RAS\ low4
tw(RH)
tw(RL)
50
55
60
ns
70 10,000 75 10,000 80 10,000 ns
Pulse duration, WE\ low
tw(WL) 10
13
15
ns
Pulse duration, TRG\ low
tw(TRG) 17
20
20
ns
Pulse duration, SC high
tw(SCH) 7
9
10
ns
Pulse duration, SC low
tw(SCL) 7
9
10
ns
Pulse duration, TRG\ high
tw(GH) 20
20
20
ns
Pulse duration, RAS\ low (page mode)
tw(RL)P 70 100,000 75 100,000 80 100,000 ns
Setup time, column address before CASx\ low
tsu(CA) 0
0
0
ns
Setup time, DSF before CASx\ low
tsu(SFC) 0
0
0
ns
Setup time, row address before RAS\ low
tsu(RA) 0
0
0
ns
Setup time, WE\ before RAS\ low
tsu(WMR) 0
0
0
ns
Setup time, DQ before RAS\ low
tsu(DQR) 0
0
0
ns
Setup time, TRG\ high before RAS\ low
tsu(TRG) 0
0
0
ns
Setup time, DSF low before RAS\ low
tsu(SFR) 0
0
0
ns
Setup time, data valid before CASx\ low
tsu(DCL) 0
0
0
ns
Setup time, data valid before WE\ low
tsu(DWL) 0
0
0
ns
Setup time, read command, WE\ high before CASx\ low
tsu(rd)
0
0
0
ns
Setup time, early-write command, WE\ low before CASx\ low
Setup time, WE\ low before CASx\ high, write
Setup time, WE\ low before RAS\ high, write
Hold time, column address after CASx\ low
Hold time, DSF after CASx\ low
Hold time, row address after RAS\ low
Hold time, TRG\ after RAS\ low
Hold time, write mask after RAS\ low
Hold time, DQ after RAS\ low (write-mask operation)
SMJ55161A
Rev. 1.6 03/05
tsu(WCL) 0
tsu(WCH) 15
tsu(WRH) 17
th(CLCA) 10
th(SFC) 12
th(RA) 10
th(TRG) 12
th(RWM) 12
th(RDQ) 12
27
0
0
ns
18
20
ns
20
20
ns
13
15
ns
15
15
ns
10
10
ns
15
15
ns
15
15
ns
15
15
ns
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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