SM55161A Datasheet, PDF (58/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
FIGURE 49: SPLIT-REGISTER OPERATING SEQUENCE
VRAM
SM55161A
Production
NOTES:
A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register-transfer cycle. This is
necessary to initialize the data register and the starting tap location. First serial access can begin either after the full-register-transfer-read cycle
(CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no
minimum requirement of SC clock between the full-register transfer-read cycle and the first split-register cycle.
B. A split-register transfer into the inactive half is not allowed until t_d(MSRL) is met. t_d(MSRL) is the minimum delay time between the rising edge of
the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register-transfer cycle into the inactive half. After the
t_d(MSRL) requirement is met, the split-register transfer into the inactive half must also satisfy the minimum t_d(RHMS) requirement. t_d(RHMS) is the
minimum delay time between the rising edge of RAS\ of the split-register-transfer cycle into the inactive half and the rising edge of the serial
clock of the last bit (bit 255 or 511).
SMJ55161A
Rev. 1.6 03/05
58
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