SM55161A Datasheet, PDF (18/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
load color register
The load-color-register cycle is performed using normal DRAM
write-cycle timing except that DSF is held high on the falling
edges of RAS\, CASL\, and CASU\. The color register is loaded
from pins DQ0 –DQ15, which are latched on either the first
falling edge of CASx\ or the falling edge of WE\, whichever
occurs later. If only one CASx\ is low, only the corresponding
byte of the color register is loaded. When the color register is
loaded, it retains data until power is lost or until another load-
color-register cycle is performed (see Figure 13 and Figure 14).
FIGURE 13: Example of Block Writes
FIGURE 14: Example Of A Persistent Block Write
Legend:
1. Refresh address
2. Row address
3. Block address (A3–A8) is latched on the first falling edge of CASx\.
4. Color-register data
5. Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS\.
6. Column-mask data: DQi–DQi+7 (i = 0, 8) are latched on either the first falling edge of CASx\ or the falling edge of WE\,
whichever occurs later.
SMJ55161A
Rev. 1.6 03/05
18
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