SM55161A Datasheet, PDF (28/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)¹
PARAMETER
Hold time, DSF after RAS\ low
Hold time, column address valid after RAS\ low⁵
Hold time, data valid after CASx\ low
Hold time, data valid after RAS\ low⁵
-70
SYMBOL MIN MAX
t_h(SFR) 10
t_h(RLCA) 30
t_h(CLD) 12
t_h(RLD) 30
-75
-80
MIN MAX MIN MAX UNIT
10
10
ns
33
35
ns
15
15
ns
35
35
ns
Hold time, data valid after WE\ low
Hold time, read, WE\ high after CASx\ high⁶
Hold time, read, WE\ high after RAS\ high⁶
Hold time, write, WE\ low after CASx\low
Hold time, write, WE\ low after RAS\ low⁵
Hold time, TRG\ high after WE\ low⁷
Hold time, SQ valid after SC high
t_h(WLD) 12
t_h(CHrd) 0
t_h(RHrd) 0
t_h(CLW) 12
t_h(RLW) 30
t_h(WLG) 10
t_h(SHSQ) 2
15
15
ns
0
0
ns
0
0
ns
15
15
ns
35
35
ns
10
10
ns
2
2
ns
Hold time, DSF after RAS\ low
t_h(RSF) 30
35
35
ns
Hold time, output valid after CASx\ low
t_h(CLQ) 0
0
0
ns
Delay time, RAS\ low to CASx\ high
Delay time, CASx\ high to RAS\ low
Delay time, CASx\ low to RAS\ high
Delay time, CASx\ low to WE\ low^9,10
Delay time, RAS\ low to CASx\ low¹¹
t_d(RLCH) 70
See Note 8 t_d(RLCH) 10
t_d(CHRL) 7
t_d(CLRH) 17
t_d(CLWL) 40
t_d(RLCL) 15
50
75
80
ns
13
15
5
5
ns
20
20
ns
48
50
ns
20 50 20 60 ns
Delay time, column address valid to RAS\ high
t_d(CARH) 35
38
40
ns
Delay time, column address valid to CASx\ high
Delay time, RAS\ low to WE\ low⁹
Delay time, column address valid to WE\ low⁹
Delay time, CASx\ low to RAS\ low⁸
Delay time, RAS\ high to CASx\ low⁸
t_d(CACH) 35
t_d(RLWL) 90
t_d(CAWL) 55
t_d(CLRL) 5
t_d(RHCL) 0
38
40
ns
100
105
ns
63
65
ns
5
5
ns
0
0
ns
Delay time, CASx\ low to TRG\ high for DRAM read cycles
t_d(CLGH) 20
20
20
ns
Delay time, TRG\ high before data applied at DQ
Delay time, RAS\ low to TRG\ high¹²
Delay time, RAS\ low to first SC high after TRG\ high¹³
Delay time, RAS\ low to column address valid
Delay time, TRG\ low to RAS\ high
Delay time, CASx\ low to first SC high after TRG\ high¹³
Delay time, SC high to TRG\ high^{12, 13}
Delay time, TRG\ high to RAS\ high¹²
Delay time, TRG\ high to RAS\ low¹⁴
Delay time, TRG\ high to SC high¹²
t_d(GHD) 15
t_d(RLTH) 55
t_d(RLSH) 70
t_d(RLCA) 12
35
t_d(GLRH) 15
t_d(CLSH) 20
t_d(SCTR) 5
t_d(THRH) -10
t_d(THRL) 50
t_d(THSC) 15
15
15
ns
58
ns
75
ns
15 35 15 40 ns
20
20
ns
23
25
ns
5
5
ns
-10
-10
ns
55
60
ns
18
20
ns
SMJ55161A
Rev. 1.6 03/05
28
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