SM55161A Datasheet, PDF (40/64 Pages) Austin Semiconductor – 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SM55161A
Production
FIGURE 33: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE TIMING
NOTES:
A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
TABLE 11: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE STATE TABLE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
STATE
1
2
3
4
5
L
L
H
Don't Care Valid Data
L
L
L
Write Mask Valid Data
L
L
L
Don't Care Valid Data
Load-write mask on either the first falling edge of CASx\
or the falling edge of WE\, whichever occurs later.¹
H
L
H
Don't Care Write Mask
NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
a don’t care during this cycle.
SMJ55161A
Rev. 1.6 03/05
40
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