ATMEGA8_08 Datasheet, PDF (71/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

ATmega8(L)
Timer/Counter
Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set. Figure 28 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value.
Figure 28. Timer/Counter Timing Diagram, No Prescaling
clk_I/O
clk_Tn
(clk_I/O/1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 29 shows the same timing data, but with the prescaler enabled.
Figure 29. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
MAX - 1
MAX
BOTTOM
TOVn
BOTTOM + 1
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