ATMEGA8_08 Datasheet, PDF (53/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

ATmega8(L)
and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 20 summarizes the control signals for the pin value.
Table 20. Port Pin Configurations
PUD
DDxn PORTxn (in SFIOR) I/O Pull-up Comment
0
0
X
Input
No Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if external
pulled low.
0
1
1
Input
No Tri-state (Hi-Z)
1
0
X
Output No Output Low (Sink)
1
1
X
Output No Output High (Source)
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register Bit. As shown in Figure 22, the PINxn Register bit and the preceding latch con-
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay. Figure 23 shows a timing dia-
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t_pd,max and t_pd,min, respectively.
Figure 23. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
XXX
in r17, PINx
0x00
t _{pd, max}
t _{pd, min}
0xFF
2486T–AVR–05/08
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows t_pd,max and t_pd,min, a single signal transition on the pin will be delayed
between ½ and 1-½ system clock period depending upon the time of assertion.
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