ATMEGA8_08 Datasheet, PDF (246/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

SPI Timing
Characteristics
5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices
connected to the Two-wire Serial Bus need only obey the general f_SCL requirement.
6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f_SCL - 2/f_CK),
thus f_CK must be greater than 6 MHz for the low time requirement to be strictly met at f_SCL =
100 kHz.
7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f_SCL - 2/f_CK),
thus the low time requirement will not be strictly met for f_SCL > 308 kHz when f_CK = 8 MHz. Still,
ATmega8 devices connected to the bus may communicate at full speed (400 kHz) with other
ATmega8 devices, as well as any other device with a proper t_LOW acceptance margin.
Figure 115. Two-wire Serial Bus Timing
SCL
SDA
t_SU;STA
t_of
t_LOW
t_HD;STA
t_HIGH
t_LOW
t_HD;DAT
t_SU;DAT
t_r
t_SU;STO
t_BUF
See Figure 116 and Figure 117 for details.
Table 102. SPI Timing Parameters
Description
Mode
1
SCK period
Master
2
SCK high/low
Master
3
Rise/Fall time
Master
4
Setup
Master
5
Hold
Master
6
Out to SCK
Master
7
SCK to out
Master
8
SCK to out high
Master
9
SS low to out
Slave
10
SCK period
11
SCK high/low⁽¹⁾
Slave
Slave
12
Rise/Fall time
Slave
13
Setup
Slave
14
Hold
Slave
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Salve
Min
4 • t_ck
2 • t_ck
10
10
20
2 • t_ck
Typ
Max
See Table 50
50% duty cycle
3.6
10
10
0.5 • t_SCK
10
10
15
ns
1.6
15
10
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2t_CLCL for f_CK < 12 MHz
- 3t_CLCL for f_CK > 12 MHz
246 ATmega8(L)
2486T–AVR–05/08