ATMEGA8_08 Datasheet, PDF (132/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure
59 and Figure 60. Data bits are shifted out and latched in on opposite edges of the SCK signal,
ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table
48 and Table 49, as done below:
Table 51. CPOL and CPHA Functionality
Leading Edge
CPOL = 0, CPHA = 0
Sample (Rising)
CPOL = 0, CPHA = 1
Setup (Rising)
CPOL = 1, CPHA = 0
Sample (Falling)
CPOL = 1, CPHA = 1
Setup (Falling)
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
SPI Mode
0
1
2
3
Figure 59. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Figure 60. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
132 ATmega8(L)
2486T–AVR–05/08