ATMEGA8_08 Datasheet, PDF (190/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

Figure 85. Formats and States in the Slave Transmitter Mode
Reception of the own
slave address and one or
S
SLA
R
A
more data bytes
DATA
A
DATA
A
P or S
$A8
$B8
$C0
Arbitration lost as master
and addressed as slave
A
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
$B0
A
All 1's P or S
$C8
From master to slave
From slave to master
DATA
n
Any number of data bytes
A
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 70.
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
Table 70. Miscellaneous States
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
0x00
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Application Software Response
To/from TWDR
To TWCR
STA STO TWINT
No TWDR action
No TWCR action
No TWDR action
0
1
1
TWEA
X
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
190 ATmega8(L)
2486T–AVR–05/08