ATMEGA8_08 Datasheet, PDF (100/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

Timer/Counter 1
Control Register B –
TCCR1B
Bit
Read/Write
Initial Value
7
ICNC1
R/W
0
6
ICES1
R/W
0
5
4
3
2
1
0
–
WGM13 WGM12 CS12
CS11
CS10
TCCR1B
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure
41 and Figure 42.
Table 40. Clock Select Bit Description
CS12 CS11 CS10 Description
0
0
0
No clock source. (Timer/Counter stopped)
0
0
1
clk_I/O/1 (No prescaling)
0
1
0
clk_I/O/8 (From prescaler)
0
1
1
clk_I/O/64 (From prescaler)
1
0
0
clk_I/O/256 (From prescaler)
1
0
1
clk_I/O/1024 (From prescaler)
1
1
0
External clock source on T1 pin. Clock on falling edge.
1
1
1
External clock source on T1 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
100 ATmega8(L)
2486T–AVR–05/08