ATMEGA8_08 Datasheet, PDF (119/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

ATmega8(L)
Timer/Counter
Register – TCNT2
Output Compare
Register – OCR2
• Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Table
46.
Table 46. Clock Select Bit Description
CS22
CS21
CS20 Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clk_T2S/(No prescaling)
0
1
0
clk_T2S/8 (From prescaler)
0
1
1
clk_T2S/32 (From prescaler)
1
0
0
clk_T2S/64 (From prescaler)
1
0
1
clk_T2S/128 (From prescaler)
1
1
0
clk_T2S/256 (From prescaler)
1
1
1
clk_T2S/1024 (From prescaler)
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
TCNT2[7:0]
TCNT2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register.
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR2[7:0]
OCR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2 pin.
Asynchronous
Operation of the
Timer/Counter
Asynchronous Status
Register – ASSR
Bit
7
6
5
4
3
2
1
0
–
–
–
–
AS2
TCN2UB OCR2UB TCR2UB
ASSR
Read/Write
R
R
R
R
R/W
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clk_I/O. When AS2 is
written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscil-
lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and
TCCR2 might be corrupted.
2486T–AVR–05/08
119