ATMEGA8_08 Datasheet, PDF (180/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

This scheme is repeated until the last byte has been sent and the transfer is ended by generat-
ing a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
1
X
0
1
X
1
0
TWIE
X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
1
X
1
0
X
1
0
TWIE
X
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the
same Slave again, or a new Slave without transmitting a STOP condition. Repeated START
enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver
mode without losing control of the bus..
Table 66. Status codes for Master Transmitter Mode
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
A START condition has been
transmitted
A repeated START condition
has been transmitted
Application Software Response
To/from TWDR
To TWCR
STA STO TWINT
Load SLA+W
0
0
1
Load SLA+W or
Load SLA+R
0
0
1
0
0
1
0x18
SLA+W has been transmitted; Load data byte or
0
0
1
ACK has been received
No TWDR action or
1
0
1
No TWDR action or
0
1
1
No TWDR action
1
1
1
0x20
SLA+W has been transmitted; Load data byte or
0
0
1
NOT ACK has been received
No TWDR action or
1
0
1
No TWDR action or
0
1
1
No TWDR action
1
1
1
0x28
Data byte has been transmitted; Load data byte or
0
0
1
ACK has been received
No TWDR action or
1
0
1
No TWDR action or
0
1
1
No TWDR action
1
1
1
0x30
Data byte has been transmitted; Load data byte or
0
0
1
NOT ACK has been received
No TWDR action or
1
0
1
No TWDR action or
0
1
1
No TWDR action
1
1
1
0x38
Arbitration lost in SLA+W or data No TWDR action or
0
0
1
bytes
No TWDR action
1
0
1
TWEA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by TWI Hardware
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Two-wire Serial Bus will be released and not addressed
Slave mode entered
A START condition will be transmitted when the bus be-
comes free
180 ATmega8(L)
2486T–AVR–05/08