ATMEGA8_08 Datasheet, PDF (208/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
Table 76. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
The ADC Data Register – ADCL and ADCH
ADLAR = 0
Bit
Read/Write
Initial Value
15
–
ADC7
7
R
R
0
0
14
–
ADC6
6
R
R
0
0
13
–
ADC5
5
R
R
0
0
12
–
ADC4
4
R
R
0
0
11
–
ADC3
3
R
R
0
0
10
–
ADC2
2
R
R
0
0
9
ADC9
ADC1
1
R
R
0
0
8
ADC8
ADC0
0
R
R
0
0
ADCH
ADCL
ADLAR = 1
Bit
Read/Write
Initial Value
15
ADC9
ADC1
7
R
R
0
0
14
ADC8
ADC0
6
R
R
0
0
13
ADC7
–
5
R
R
0
0
12
ADC6
–
4
R
R
0
0
11
ADC5
–
3
R
R
0
0
10
ADC4
–
2
R
R
0
0
9
ADC3
–
1
R
R
0
0
8
ADC2
–
0
R
R
0
0
ADCH
ADCL
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on
page 205.
208 ATmega8(L)
2486T–AVR–05/08