ATMEGA8_08 Datasheet, PDF (235/308 Pages) ATMEL Corporation – 8-bit with 8K Bytes In-System Programmable Flash

2486T–AVR–05/08
ATmega8(L)
Figure 111. Parallel Programming Timing, Reading Sequence (within the same Page) with Tim-
ing Requirements⁽¹⁾
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
t_XLOL
t_BVDV
BS1
OE
t_OLDV
t_OHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 109 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to read-
ing operation.
Table 95. Parallel Programming Characteristics, V_CC = 5V ± 10%
Symbol Parameter
Min Typ
V_PP
I_PP
t_DVXH
t_XLXH
t_XHXL
t_XLDX
t_XLWL
t_XLPH
t_PLXH
t_BVPH
t_PHPL
t_PLBX
t_WLBX
t_PLWL
t_BVWL
t_WLWH
t_WLRL
t_WLRH
t_{WLRH_CE}
t_XLOL
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High⁽¹⁾
WR Low to RDY/BSY High for Chip Erase⁽²⁾
XTAL1 Low to OE Low
11.5
67
200
150
67
0
0
150
67
150
67
67
67
67
150
0
3.7
7.5
0
Max
12.5
250
1
4.5
9
Units
V
μA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ms
ms
ns
235