EPM240 Datasheet, PDF (81/86 Pages) Altera Corporation – JTAG & In-System Programmability

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–23
JTAG Timing Specifications
Figure 5–6 shows the timing waveforms for the JTAG signals.
Figure 5–6. MAX II JTAG Timing Waveforms
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t_JPH
t_JPXZ
t_JSXZ
Table 5–31 shows the JTAG Timing parameters and values for MAX II devices.
Table 5–31. MAX II JTAG Timing Parameters (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
t_JCP (1)
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
TCK clock period for V_CCIO1 = 3.3 V
TCK clock period for V_CCIO1 = 2.5 V
TCK clock period for V_CCIO1 = 1.8 V
TCK clock period for V_CCIO1 = 1.5 V
TCK clock high time
55.5
—
ns
62.5
—
ns
100
—
ns
143
—
ns
20
—
ns
TCK clock low time
20
—
ns
JTAG port setup time (2)
8
—
ns
JTAG port hold time
10
—
ns
JTAG port clock to output (2)
—
15
ns
JTAG port high impedance to valid output (2)
—
15
ns
JTAG port valid output to high impedance (2)
—
15
ns
Capture register setup time
8
—
ns
Capture register hold time
10
—
ns
Update register clock to output
—
25
ns
© Novermber 2008 Altera Corporation
MAX II Device Handbook