EPM240 Datasheet, PDF (72/86 Pages) Altera Corporation – JTAG & In-System Programmability

5–14
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 2)
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed
Grade
Grade
Grade
Grade
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Unit
t_ACLK
Address register clock period
100 — 100 — 100 — 100 — 100 — ns
t_ASU
Address register shift signal setup 20 — 20 — 20 — 20 — 20 — ns
to address register clock
t_AH
Address register shift signal hold to 20 — 20 — 20 — 20 — 20 — ns
address register clock
t_ADS
Address register data in setup to
20 — 20 — 20 — 20 — 20 — ns
address register clock
t_ADH
Address register data in hold from 20 — 20 — 20 — 20 — 20 — ns
address register clock
t_DCLK
Data register clock period
100 — 100 — 100 — 100 — 100 — ns
t_DSS
Data register shift signal setup to 60 — 60 — 60 — 60 — 60 — ns
data register clock
t_DSH
Data register shift signal hold from 20 — 20 — 20 — 20 — 20 — ns
data register clock
t_DDS
Data register data in setup to data 20 — 20 — 20 — 20 — 20 — ns
register clock
t_DDH
Data register data in hold from data 20 — 20 — 20 — 20 — 20 — ns
register clock
t_DP
Program signal to data clock hold 0 — 0 — 0 — 0 — 0 — ns
time
t_PB
Maximum delay between program — 960 — 960 — 960 — 960 — 960 ns
rising edge to UFM busy signal
rising edge
t_BP
Minimum delay allowed from UFM 20 — 20 — 20 — 20 — 20 — ns
busy signal going low to program
signal going low
t_PPMX
Maximum length of busy pulse
during a program
— 100 — 100 — 100 — 100 — 100 µs
t_AE
Minimum erase signal to address
0 — 0 — 0 — 0 — 0 — ns
clock hold time
t_EB
Maximum delay between the erase — 960 — 960 — 960 — 960 — 960 ns
rising edge to the UFM busy signal
rising edge
t_BE
Minimum delay allowed from the 20 — 20 — 20 — 20 — 20 — ns
UFM busy signal going low to erase
signal going low
t_EPMX
Maximum length of busy pulse
during an erase
— 500 — 500 — 500 — 500 — 500 ms
t_DCO
Delay from data register clock to
— 5 — 5 — 5 — 5 — 5 ns
data register output
MAX II Device Handbook
© Novermber 2008 Altera Corporation