EPM240 Datasheet, PDF (18/86 Pages) Altera Corporation – JTAG & In-System Programmability

2–10
Chapter 2: MAX II Architecture
Logic Elements
The other two LUTs use the data1 and data2 signals to generate two possible carry-out
signals: one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts
as the carry-select for the carry-out0 output and carry-in1 acts as the carry-
select for the carry-out1 output. LEs in arithmetic mode can drive out registered
and unregistered versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable, synchronous
up/down control, synchronous clear, synchronous load, and dynamic
adder/subtractor options. The LAB local interconnect data inputs generate the
counter enable and synchronous up/down control signals. The synchronous clear
and synchronous load options are LAB-wide signals that affect all registers in the
LAB. The Quartus II software automatically places any registers that are not used by
the counter into other LABs. The addnsub LAB-wide signal controls whether the LE
acts as an adder or subtractor.
Figure 2–8. LE in Dynamic Arithmetic Mode
LAB Carry-In
Carry-In0
Carry-In1
addnsub
(LAB Wide)
(1)
sload
sclear
(LAB Wide) (LAB Wide)
Register chain
connection
aload
(LAB Wide)
data1
data2
data3
LUT
ALD/PRE
ADATA Q
D
LUT
ENA
CLRN
clock (LAB Wide)
LUT
ena (LAB Wide)
aclr (LAB Wide)
LUT
Register Feedback
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register
chain output
Carry-Out0 Carry-Out1
Note to Figure 2–8:
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between LEs in
dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation
to increase the speed of carry functions. The LE is configured to calculate outputs for a
possible carry-in of 0 and carry-in of 1 in parallel. The carry-in0 and carry-in1
signals from a lower-order bit feed forward into the higher-order bit via the parallel
carry chain and feed into both the LUT and the next portion of the carry chain. Carry-
select chains can begin in any LE within an LAB.
MAX II Device Handbook
© October 2008 Altera Corporation