EPM240 Datasheet, PDF (76/86 Pages) Altera Corporation – JTAG & In-System Programmability

5–18
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–23 shows the external I/O timing parameters for EPM240 devices.
Table 5–23. EPM240 Global Clock External I/O Timing Parameters
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Unit
t_PD1
Worst case
pin-to-pin
10 pF — 4.7 — 6.1 — 7.5 — 7.9 — 12.0 ns
delay through
1 look-up
table (LUT)
t_PD2
Best case pin- 10 pF — 3.7 — 4.8 — 5.9 — 5.8 — 7.8 ns
to-pin delay
through
1 LUT
t_SU
Global clock
—
1.7 — 2.2 — 2.7 — 2.8 — 4.7 — ns
setup time
t_H
Global clock
—
0.0 — 0.0 — 0.0 — 0 — 0 — ns
hold time
t_CO
Global clock
10 pF 2.0 4.3 2.0 5.6 2.0 6.9 2.0 7.7 2.0 10.5 ns
to output
delay
t_CH
Global clock
—
166 — 216 — 266 — 253 — 335 — ps
high time
t_CL
Global clock
—
166 — 216 — 266 — 253 — 335 — ps
low time
t_CNT
Minimum
global clock
—
3.3 — 4.0 — 5.0 — 5.4 — 8.1 — ns
period for
16-bit counter
f_CNT
Maximum
global clock
—
— 304.0 — 247.5 — 201.1 — 184.1 — 123.5 MHz
(1)
frequency for
16-bit counter
Note to Table 5–23:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
MAX II Device Handbook
© Novermber 2008 Altera Corporation