EPM240 Datasheet, PDF (68/86 Pages) Altera Corporation – JTAG & In-System Programmability

5–10
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–13. MAX II Device Timing Model Status
Device
Preliminary
Final
EPM1270
—
v
EPM2210
—
v
Note to Table 5–13:
(1) The MAX IIZ device timing models are only available in the Quartus II software version
8.0 and later.
Performance
Table 5–14 shows the MAX II device performance for some common designs. All
performance values were obtained with the Quartus II software compilation of
megafunctions. Performance values for –3, –4, and –5 speed grades are based on an
EPM1270 device target while –6 and –7 speed grades are based on an EPM570Z device
target.
Table 5–14. MAX II Device Performance
Resources Used
Performance
Resource Design Size and
Used
Function
Mode
–3
–4
–5
–6
–7
UFM Speed Speed Speed Speed Speed
LEs Blocks Grade Grade Grade Grade Grade Unit
LE
16-bit counter (1)
—
16
0
304.0 247.5 201.1 184.1 123.5 MHz
64-bit counter (1)
—
64
0
201.5 154.8 125.8 83.2 83.2 MHz
16-to-1 multiplexer
—
11
0
6.0
8.0
9.3 17.4 17.3 ns
32-to-1 multiplexer
—
24
0
7.1
9.0 11.4 12.5 22.8 ns
16-bit XOR function
—
5
0
5.1
6.6
8.2
9.0 15.0 ns
16-bit decoder with
—
5
0
5.2
6.6
8.2
9.2 15.0 ns
single address line
UFM
512 × 16
None
3
1
10.0 10.0 10.0 10.0 10.0 MHz
512 × 16
SPI (2) 37
1
8.0
8.0
8.0
9.7
9.7 MHz
512 × 8
Parallel (3) 73
1
(4)
(4)
(4)
(4)
(4) MHz
512 × 16
I²C (3)
142
1 100 (5) 100 (5) 100 (5) 100 (5) 100 (5) kHz
Notes to Table 5–14:
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of LEs used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I²C megafunction is verified in hardware up to 100-kHz serial clock line (SCL) rate.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device
density. Table 5–15 through Table 5–22 describe the MAX II device internal timing
microparameters for logic elements (LEs), input/output elements (IOEs), UFM
structures, and MultiTrack interconnects. The timing values for –3, –4, and –5 speed
grades shown in Table 5–15 through Table 5–22 are based on an EPM1270 device
target, while –6 and –7 speed grade values are based on an EPM570Z device target.
MAX II Device Handbook
© Novermber 2008 Altera Corporation