EPM240 Datasheet, PDF (79/86 Pages) Altera Corporation – JTAG & In-System Programmability

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–21
External Timing I/O Delay Adders
The I/O delay timing parameters for I/O standard input and output adders, and
input delays are specified by speed grade independent of device density.
Table 5–27 through Table 5–28 show the adder delays associated with I/O pins for all
packages. The delay numbers for –3, –4, and –5 speed grades shown in Table 5–27
through Table 5–30 are based on an EPM1270 device target, while –6 and –7 speed
grade values are based on an EPM570Z device target. If an I/O standard other than
3.3-V LVTTL is selected, add the input delay adder to the external t_SU timing
parameters shown in Table 5–23 through Table 5–26. If an I/O standard other than
3.3-V LVTTL with 16 mA drive strength and fast slew rate is selected, add the output
delay adder to the external t_CO and t_PD shown in Table 5–23 through Table 5–26.
Table 5–27. External Timing Input Delay Adders
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Standard
Min Max Min Max Min Max Min Max Min Max Unit
3.3-V LVTTL Without Schmitt — 0 — 0 — 0 — 0 — 0 ps
Trigger
With
— 334 — 434 — 535 — 387 — 434 ps
Schmitt Trigger
3.3-V
LVCMOS
Without Schmitt — 0 — 0 — 0 — 0 — 0 ps
Trigger
With
— 334 — 434 — 535 — 387 — 434 ps
Schmitt Trigger
2.5-V LVTTL Without Schmitt — 23 — 30 — 37 — 42 — 43 ps
Trigger
With Schmitt
Trigger
— 339 — 441 — 543 — 429 — 476 ps
1.8-V LVTTL Without Schmitt — 291 — 378 — 466 — 378 — 373 ps
Trigger
1.5-V LVTTL Without Schmitt — 681 — 885 — 1,090 — 681 — 622 ps
Trigger
3.3-V PCI Without Schmitt — 0 — 0 — 0 — 0 — 0 ps
Trigger
Table 5–28. MAX II IOE Programmable Delays
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Parameter
Min Max Min Max Min Max Min Max Min Max Unit
Input Delay from Pin to Internal — 1,225 — 1,592 — 1,960 — 1,858 — 2,171 ps
Cells = 1
Input Delay from Pin to Internal — 89 — 115 — 142 — 569 — 609 ps
Cells = 0
© Novermber 2008 Altera Corporation
MAX II Device Handbook