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EPM240 Datasheet, PDF (4/86 Pages) Altera Corporation – JTAG & In-System Programmability | |||
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1â2
Chapter 1: Introduction
Features
Table 1â1 shows the MAX II family features.
Table 1â1. MAX II Family Features
Feature
EPM240 EPM570 EPM1270
EPM240G EPM570G EPM1270G
EPM2210
EPM2210G
EPM240Z EPM570Z
LEs
240
570
1,270
2,210
240
570
Typical Equivalent Macrocells
192
440
980
1,700
192
440
Equivalent Macrocell Range 128 to 240 240 to 570 570 to 1,270 1,270 to 2,210 128 to 240 240 to 570
UFM Size (bits)
8,192
8,192
8,192
8,192
8,192
8,192
Maximum User I/O pins
80
160
212
272
80
160
tPD1 (ns) (1)
4.7
5.4
6.2
7.0
7.5
9.0
fCNT (MHz) (2)
304
304
304
304
152
152
tSU (ns)
1.7
1.2
1.2
1.2
2.3
2.2
tCO (ns)
4.3
4.5
4.6
4.6
6.5
6.7
Notes to Table 1â1:
(1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic
implemented in a single LUT and LAB that is adjacent to the output pin.
(2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number.
f For more information about equivalent macrocells, refer to the MAX II Logic Element to
Macrocell Conversion Methodology white paper.
MAX II and MAX IIG devices are available in three speed grades: â3, â4, and â5, with
â3 being the fastest. Similarly, MAX IIZ devices are available in two speed grades: â6,
â7, with â6 being faster. These speed grades represent the overall relative
performance, not any specific timing parameter. For propagation delay timing
numbers within each speed grade and density, refer to the DC and Switching
Characteristics chapter in the MAX II Device Handbook.
Table 1â2 shows MAX II device speed-grade offerings.
Table 1â2. MAX II Speed Grades
Speed Grade
Device
EPM240
EPM240G
EPM570
EPM570G
EPM1270
EPM1270G
EPM2210
EPM2210G
EPM240Z
EPM570Z
â3
â4
â5
â6
â7
v
v
v
â
â
v
v
v
â
â
v
v
v
â
â
v
v
v
â
â
â
â
â
v
v
â
â
â
v
v
MAX II Device Handbook
© October 2008 Altera Corporation
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