EPM240 Datasheet, PDF (78/86 Pages) Altera Corporation – JTAG & In-System Programmability

5–20
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–25. EPM1270 Global Clock External I/O Timing Parameters (Part 2 of 2)
–3 Speed Grade –4 Speed Grade –5 Speed Grade
Symbol
Parameter
Condition Min
Max
Min Max Min Max Unit
t_CNT
Minimum global clock
—
3.3
—
4.0
—
5.0
—
ns
period for
16-bit counter
f_CNT
Maximum global clock
—
— 304.0 (1) — 247.5 — 201.1 MHz
frequency for 16-bit
counter
Note to Table 5–25:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
Table 5–26 shows the external I/O timing parameters for EPM2210 devices.
Table 5–26. EPM2210 Global Clock External I/O Timing Parameters
–3 Speed Grade –4 Speed Grade –5 Speed Grade
Symbol
Parameter
Condition Min Max Min Max Min Max Unit
t_PD1
Worst case pin-to-pin delay 10 pF
—
7.0
—
9.1
— 11.2 ns
through 1 look-up table
(LUT)
t_PD2
Best case pin-to-pin delay
10 pF
—
3.7
—
4.8
—
5.9
ns
through 1 LUT
t_SU
Global clock setup time
—
1.2
—
1.5
—
1.9
—
ns
t_H
Global clock hold time
—
0.0
—
0.0
—
0.0
—
ns
t_CO
Global clock to output delay 10 pF
2.0
4.6
2.0
6.0
2.0
7.4
ns
t_CH
Global clock high time
—
166
—
216
—
266
—
ps
t_CL
Global clock low time
—
166
—
216
—
266
—
ps
t_CNT
Minimum global clock
period for
16-bit counter
—
3.3
—
4.0
—
5.0
—
ns
f_CNT
Maximum global clock
—
— 304.0 — 247.5 — 201.1 MHz
frequency for 16-bit counter
(1)
Note to Table 5–26:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
MAX II Device Handbook
© Novermber 2008 Altera Corporation