EPM240 Datasheet, PDF (80/86 Pages) Altera Corporation – JTAG & In-System Programmability

5–22
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Maximum Input and Output Clock Rates
Table 5–29 and Table 5–30 show the maximum input and output clock rates for
standard I/O pins in MAX II devices.
Table 5–29. MAX II Maximum Input Clock Rate for I/O
Standard
3.3-V LVTTL
Without Schmitt
Trigger
With Schmitt
Trigger
3.3-V LVCMOS
Without Schmitt
Trigger
With Schmitt
Trigger
2.5-V LVTTL
Without Schmitt
Trigger
With Schmitt
Trigger
2.5-V LVCMOS
Without Schmitt
Trigger
With Schmitt
Trigger
1.8-V LVTTL
Without Schmitt
Trigger
1.8-V LVCMOS
Without Schmitt
Trigger
1.5-V LVCMOS
Without Schmitt
Trigger
3.3-V PCI
Without Schmitt
Trigger
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed
Grade
Grade
Grade
Grade
Grade Unit
304
304
304
304
304
MHz
250
250
250
250
250
MHz
304
304
304
304
304
MHz
250
250
250
250
250
MHz
220
220
220
220
220
MHz
188
188
188
188
188
MHz
220
220
220
220
220
MHz
188
188
188
188
188
MHz
200
200
200
200
200
MHz
200
200
200
200
200
MHz
150
150
150
150
150
MHz
304
304
304
304
304
MHz
Table 5–30. MAX II Maximum Output Clock Rate for I/O
Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V PCI
–3 Speed
–4 Speed
–5 Speed
–6 Speed
–7 Speed
Grade
Grade
Grade
Grade
Grade
Unit
304
304
304
304
304
MHz
304
304
304
304
304
MHz
220
220
220
220
220
MHz
220
220
220
220
220
MHz
200
200
200
200
200
MHz
200
200
200
200
200
MHz
150
150
150
150
150
MHz
304
304
304
304
304
MHz
MAX II Device Handbook
© Novermber 2008 Altera Corporation