EPM240 Datasheet, PDF (30/86 Pages) Altera Corporation – JTAG & In-System Programmability

2–22
Figure 2–17. EPM570, EPM1270, and EPM2210 UFM Block LAB Row Interface
Chapter 2: MAX II Architecture
MultiVolt Core
CFM Block
RTP_BUSY
BUSY
OSC
DRDout
DRDin
LAB
DRDCLK
DRDSHFT
ARDin
PROGRAM
ERASE
OSC_ENA
ARCLK
LAB
ARSHFT
UFM Block
LAB
MultiVolt Core
The MAX II architecture supports the MultiVolt core feature, which allows MAX II
devices to support multiple V_CC levels on the V_CCINT supply. An internal linear voltage
regulator provides the necessary 1.8-V internal voltage supply to the device. The
voltage regulator supports 3.3-V or 2.5-V supplies on its inputs to supply the 1.8-V
internal voltage to the device, as shown in Figure 2–18. The voltage regulator is not
guaranteed for voltages that are between the maximum recommended 2.5-V
operating voltage and the minimum recommended 3.3-V operating voltage.
The MAX IIG and MAX IIZ devices use external 1.8-V supply. The 1.8-V V_CC external
supply powers the device core directly.
Figure 2–18. MultiVolt Core Feature in MAX II Devices
3.3-V or 2.5-V on
VCCINT Pins
Voltage
Regulator
1.8-V on
VCCINT Pins
1.8-V Core
Voltage
1.8-V Core
Voltage
MAX II Device
MAX IIG or MAX IIZ Device
MAX II Device Handbook
© October 2008 Altera Corporation